For the case of an ADC capable of performing the function of quantizing an analog voltage value into a digital voltage value, conversion precision (resolution and differential non linearity error), conversion frequency, and power consumption are most important characteristics. The problems is that these characteristics conflict with one anther and thus various types of ADCs have been developed to applications.
ADCs have been finding applications in image processing, and in particular they are often applied to video cameras of a portable type for signal processing. Such a video camera (conversion frequency: in vicinity of 20 MHz for processing image sensor output signals) must be designed to operate with less power because it is battery-powered.
Referring now to FIG. 9, the organization of a conventional ADC is described. A sampling circuit 77, composed of a capacitor and a buffer circuit, samples an analog voltage. A voltage amplifier 78 amplifies the voltage difference between a sampled analog voltage and a reference voltage. Such an amplified voltage difference is amplified by a logical-level amplifier 10 to a logical-level voltage and is converted by a logic device 11 into an A/D conversion output 12.
One example of these ADCs for use in image processing equipment is shown in FIG. 11, which is a monolithic type composed of CMOS transistors. Prior to describing analog-to-digital conversion, the operation of a voltage comparator, which is one of the components of the ADC, is explained. A lower voltage comparator 96 has switches SW5, SW6, SW7, and SW8. These switches can be configurated by PMOS transfer gates, by NMOS transfer gates, or by CMOS transfer gates. One of the terminals of SW6 is connected to an analog signal 1 and the other is connected to a capacitor C1. One of the terminals of SW5 is connected to a reference resistor/switch row 84 and the other is connected to one of the terminals of C1 to which SW6 is connected. The other terminal of C1 is connected to an input terminal of an inverter 82. An inverter 83 and inverter 97 are provided. These inverters including the inverter 82 can be formed by CMOS inverters, by E/D inverters, or by E/E inverters. One of the terminals of SW7 is connected to the input terminal of the inverter 82 and the other is connected to an output terminal of the Inverter 82. One of the terminals of a capacitor C2 is connected to an input terminal of the inverter 83 and the other is connected to the output terminal of the inverter 82. One of the terminals of SW8 is connected to the output terminal of the inverter 83 and the other terminal is connected to an output terminal of the inverter 83. The output terminal of the inverter 83 is connected to an input terminal of the inverter 97. This is the organization of the lower voltage comparator 96.
Next, the operation is described. FIG. 16 is a diagram with regard to the timing of SW5, SW6, SW7, and SW8. In this timing diagram, each switch is in the ON-state when a clock is at high level, whereas each switch is in the OFF-state when a clock is at low level. During the sample period, SW6, SW7, and SW8 each enter the ON-state. This connects the analog signal 1 and C1, as a result of which the voltage of the analog signal 1 is applied to one of the terminals of C1. A voltage value of V.sub.a appears at the other terminal of C1. This is explained as follows. Since SW7 is in the ON-state, voltages at the input and output terminals of the inverter 82 are V.sub.a (i.e. the voltage value at the point where the inverter input/output static characteristic curve and the straight line where the input voltage and the output voltage become the same cross) (see FIG. 19). Likewise, since SW8 is in the ON-state, voltages at the input and output terminals of the inverter 88 are V.sub.a. Next, during the hold period, SW6, SW7, and SW8 are in the OFF-state. At this point, analog voltage is held at C1. In other words, the voltage across C1 becomes, at the time when the timing enters the hold period, the voltage difference between the analog voltage held and V.sub.a is held by C1.
The relationship between the storage electric charge of a parallel-plate capacitor and the terminal voltage difference is applicable to the case where the voltage difference held at Ci=the amount of electric charge Q1, then EQU Q1=C1(V.sub.in -V.sub.a) (1)
where C1 is the value of capacitance of C1 and V.sub.in is the analog voltage held.
Next, at the comparison period, when SW5 enters the ON-state, the voltage difference between a voltage of V.sub.b at the input terminal of the inverter 82 and a reference voltage of V.sub.ref is applied across C1. Since SW7 is in the OFF-state and the input terminal of the inverter 82 is a MOS transistor gate, the input impedance is great. Thus, the entering and leaving gate currents can be ignored. Since the electric charge of the input terminal of the inverter 82 has been held since the hold period, this allows the following formula to hold: EQU Q1=C1(V.sub.ref -V.sub.b) (2)
where V.sub.ref is the reference voltage. When the formula (1) is substituted in the formula (2) so as to eliminate Q1, V.sub.b is: EQU V.sub.b =V.sub.ref -V.sub.in +V.sub.a ( 3)
With regard to the input terminal of the inverter 82, V.sub.ref -V.sub.in varies more than V.sub.a. Accordingly, the output voltage of the inverter 82 (i.e. V.sub.of) is given by: EQU V.sub.of =Gf(V.sub.ref -V.sub.in)+V.sub.a ( 4) EQU Gf&lt;-1
where Gf is the voltage gain of the inverter 82 (see FIG. 19). Also, in the inverter 83, its input voltage is amplified in the same way. Since the voltage variable from V.sub.a of the inverter 83 becomes the amount of change from V.sub.a of V.sub.of of the inverter 82, an output voltage of V.sub.os is: EQU V.sub.os =Gf.multidot.Gs(V.sub.ref -V.sub.in)+V.sub.a ( 5) EQU Gs&lt;-1
where Gs is the voltage gain of the inverter 83.
The formula (5) shows that V.sub.os is proportional to V.sub.ref -V.sub.in, and that Gf.multidot.Gs is the proportional coefficient. In other words, the voltage difference between the reference voltage V.sub.ref and the sampled analog signal voltage V.sub.in is amplified Gf.multidot.Gs times and is output. The resulting voltage, that is, V.sub.os is further amplified by the inverter 97 to a logical-level voltage and then is output as a voltage comparison result.
Next, the entire ADC, shown in FIG. 11, is described. This ADC is a 5-bit series-parallel ADC with two bits for upper voltage comparison range and the remaining three bits for lower voltage comparison range. This ADC has an upper comparator row 79, formed by a group of upper voltage comparators, for comparing voltages in the upper voltage comparison range, lower comparator rows 80 and 94, each formed by a group of lower voltage comparators, for comparing voltages in the lower voltage comparison range, a reference resistor/switch row 84 capable of performing the function of applying comparison results produced by the upper comparator row 79 to the lower comparator rows 80 and 94, an upper logic device 86, lower logic devices 87 and 95, and an adder 88. Connection among these elements is described. Terminals of switches SW2 of the upper voltage comparator group are connected to capacitors C1 and the other terminals of SW2's are connected to 1/4, 2/4, and 3/4 division points produced by dividing a reference voltage 2a and reference voltage 2b by using a reference resistor row 98. Each SW1 of the upper voltage comparator group is connected to the analog signal 1. An output terminal of the upper comparator row 79 is connected to the upper logic device 86. Each SW5 of the lower comparator row 80 is connected to switch rows 85, and 91 to 93. Each SW6 of the row 80 is connected to the analog signal 1. The lower comparator row 80 is connected to the lower logic device 87. Connection as to voltage comparators constituting the lower comparator row 94 is the same. In the switch rows 85 and 91 to 93, switches are connected to 1/8, 2/8, 3/8, 4/8, 5/8, 6/8, 7/8 division points of the upper voltage comparison range. The upper logic device 86, lower logic device 87, and lower logic device 95 are connected to the adder 88. Further, the adder 88 sends out an A/D conversion output 89.
The operation contents of an upper voltage comparator is described in FIG. 16. FIG. 16 also shows the operation contents of a lower voltage comparator. During the sample period, SW1, SW3, and SW4 of the upper voltage comparator group, and SW6, SW7, and SW8 of the lower voltage comparator group each have an ON-state. Both the upper voltage comparator group and the lower voltage comparator group, therefore, sample analog signal voltages in common. Then, the upper voltage comparator group enter the upper comparison period, during which period SW1, SW3, and SW4 are in the OFF-state and SW2 is in the ON-state. The upper voltage comparator group output upper comparison results based on which the upper logic circuit 86 sends out either one of signals S1, S2, S3, and S4 so as to select one of the switch rows 85, 91, 92, and 93. When the upper voltage comparator group remain in the upper comparison period, the first lower voltage comparator group (i.e. the lower comparator row 80) are in the hold period and have to hold analog voltage until the upper voltage comparator group output comparison results so as to determine the lower voltage comparison range. When the lower voltage comparison range is determined, the timing now enters the lower comparison period. Then, SW5's of the first lower voltage comparator group are connected to one of the Switch rows 85, 91, 92, and 93 selected according to comparison results produced by the upper voltage comparison group. The first lower voltage comparator group output lower comparison results. The upper comparison result becomes 2-bit data at the upper logic device 86, whereas the lower comparison result becomes 3-bit data at the first lower logic device 87. The adder 88 adds these two items of data and outputs the sum, i.e. a 5-bit A/D conversion output 89.
In order to execute the above-described operation, the upper voltage comparator group carry out one-cycle conversion and thus one period of a reference clock is required. Since the lower voltage comparator group carry out conversion after the lower voltage comparator range is fixed, one cycle of a reference clock must be taken for the lower voltage comparator comparison period. As a result, the sampling of analog signal voltage is carried out before carrying out upper and lower operations. This indicates that two cycles of a reference clock is needed until the results of comparison is output. In order to output both the results of upper comparison and the results of lower comparison by one cycle of a reference clock, the additional provision of the second lower comparator row 94 is required. The first and second lower comparator rows 80 and 94 operate in turn. More specifically, when the first lower comparator row 84 enters the lower comparison period, the second lower comparison row 94 enters the sample period. Since, at this point in time, the upper comparator row 79 has already given upper comparison results used to determine the first lower comparator row's 80 lower comparison range, the upper comparator row 79 and second lower comparator row 94 sample analog signal voltages in common. The subsequent operation is the same as the operation of the upper comparator row 79, and as the operation of the first lower comparator row 80. Since two comparator rows, that is, the first and second lower comparator rows 80 and 94 operate in turn, this makes it possible to output the A/D conversion output 89 for every one period of a reference clock.
Incidentally, voltage comparator comparison precision is dependent on the threshold voltage of the change point of ADC digital output results. The drop in comparison precision results in the degradation in differential non linearity error. In order to obtain adequate comparison precision, it is important to reduce the amount of amplification by means of logical-level amplification for amplifying the voltage difference between an analog voltage and a reference voltage to a logical-level and to take a longer amplification time.
Switches SW5, SW6, SW7, and SW8, which are components of the lower voltage comparator 96, can take the form of NMOS transfer gates, of PMOS transfer gates, or of CMOS transfer gates. By the application of a clock signal (hereinafter called the switch control signal) to the gate of a MOS transistor, these transfer gates perform the function of switching between an ON-state (drain-to-source conduction) and an OFF-state (non-conduction). One of the characteristics of transfer gates is a phenomenon known as feedthrough. When a switch control signal makes a transition from ON-state voltage level to OFF-state voltage level (or from OFF-state voltage level to ON-state voltage level) due to the gate-to-drain capacitance (or gate-to-source capacitance) of a MOS transistor, it undergoes alternate current coupling and thus electric charge is implanted into the drain (or source), which is know as the feedthrough. In an operation for holding an analog input signal voltage of V.sub.in at the time when transition is made from the sample state to the hold state, when SW6. SW7, and SW8 make a transition to the OFF-state, electric charge is implanted or extracted into or from the connection of capacitor C1 and the inverter 82, and into or from the connection of capacitor C2 and the inverter 83. As a result, errors occur to V.sub.in. The amount of implanted electric charge by feedthrough depends much upon the value of drain voltage (or source voltage) of MOS transistors, the gate length, the gate width, and the threshold voltage (hereinafter these being called the device parameters). The ADC requires a great number of voltage comparators, and differential non linearity error relates to the matching of device parameters. If the amounts of electric charge being implanted to voltage comparators vary due to device parameter variations, this causes holding voltages to vary. This gives rise to the degradation of differential non linearity error. It is already described that the degradation of differential non linearity error occurs even in a single lower comparator row due to holding voltage variations. For the case of employing two lower comparator rows (FIG. 11), holding voltage variation occurs even between the two rows. A further problem arises that the degradation of differential non linearity error becomes more serious. Since holding voltage error due to feedthrough degrades the voltage comparison precision of a group of voltage comparators, this determines minimum voltage comparison range thereby determining the limit of ADC resolution. Further, since all of the three inverters used in a voltage comparator are biased to V.sub.a during the sample period as well as during the hold period, this increases the total amount of passing-through current (see FIG. 19). As a result, consumption power becomes increased.